Dual-Port Static Random Access Memory (DP-SRAM) provides more bandwidth than single-port SRAM (SP-SRAM) because DP-SRAM provides for at least two independent ports for addressing the same bit-cell in the SRAM. As such, the same bit-cell can be simultaneously read by the two different ports, and two different bit-cells in a same row of the DP-SRAM array can be written to with different data. Because of having more bandwidth, the demand for DP-SRAM is increasing relative to the demand for SP-SRAM. However, DP-SRAM presents its own challenges, which may not exist in the SP-SRAM.
For example, during normal dual port operation, two word-lines (WLs) of a row or column of the DP-SRAM can be simultaneously activated (i.e., turned on) and may cause a read or write failure in the bit-cells of that row or column. This failure is traditionally referred to as the “disturb issue.” The disturb issue reduces the read and writes margins of the DP-SRAM. The disturb issue also increases the minimum operating voltage of the DP-SRAM (Vmin).